1. Field of the Invention
The present invention relates to a high-frequency switching apparatus that performs, for example, switching between on and off states of a signal path or between a plurality of signal paths in a mobile communication device and the like.
2. Description of the Background Art
FIG. 17 is an equivalent circuit diagram of a SPDT (Single-Pole Double-Throw) high-frequency switching apparatus which is one of conventional art high-frequency switching apparatuses (see, for example, page 4 and FIG. 1 of Japanese Laid-Open Patent Publication No. 8-139014). In FIG. 17, reference numerals FET11 to FET14 and FET21 to FET24 each denote a depression-type field-effect transistor (hereinafter, simply referred to as a “field-effect transistor”). Reference numerals Rt11 to Rt14 and Rt21 to Rt24 each denote a resistor. Reference numeral IN11 denotes a signal input terminal. Reference numerals OUT11 and OUT12 denote a first and a second signal output terminals, respectively. Reference numerals Vcnt11 and Vcnt12 denote a first and a second control voltage terminals, respectively. Reference numeral TF11 denotes a first transfer circuit. Reference numeral TF12 denotes a second transfer circuit.
In this configuration, when, for example, a voltage of 3 volts and a voltage of 0 volt are applied to the first control voltage terminal Vcnt11 and the second control voltage terminal Vcnt12, respectively, the field-effect transistors FET11 to FET14 go into anon state and the field-effect transistors FET21 to FET24 go into an off state. This makes it possible to bring a path from the signal input terminal IN11 to the signal output terminal OUT11 into a conduction state (on path) and to bring a path from the signal input terminal IN11 to the signal output terminal OUT12 into a cutoff state (off path).
In the above conventional art configuration, although in the off path the field-effect transistors FET21 to FET24 are in the off state, when a large signal of 30 dBm or more is used, a signal leaking to the second signal output terminal OUT12 through the field-effect transistors FET21 to FET24 is great. Thus, the isolation characteristics are poor and an apparatus that is connected to a stage subsequent to the second signal output terminal OUT12 and that composes a receiving circuit and the like may possibly break down.
On page 4 and in FIG. 1 of Japanese Laid-Open Patent Publication No. 8-213893, to circumvent such a problem, as shown in FIG. 18, shunt circuit units SH11 and SH12 are connected to a first and a second signal output terminals OUT11 and OUT12, respectively, and ends of the respective shunt circuit units SH11 and SH12 are connected to ground GND via DC cut capacitors C12 and C13, respectively. The shunt circuit units SH11 and SH12 are controlled to be in opposite phase to their corresponding transfer circuit units TF11 and TF12 present in paths leading to the signal output terminals OUT11 and OUT12, respectively. By this, signals leaking from the transfer circuit units TF11 and TF12 flow to the ground GND, making it possible to prevent the signals from flowing into a receiving circuit and the like.
However, since inductance components, such as a package and wires, are added between the ground GND and the capacitors C12 and C13 or between the ground GND and field-effect transistors FET15 and FET25 to which the capacitors C12 and C13 are connected, respectively, excellent isolation characteristics cannot be obtained. Besides, capacitors formed by a semiconductor process have a problem that the ESD breakdown voltage (electrostatic breakdown voltage) significantly deteriorates.